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IEEE PROJECTS LIST - YEAR OF 2021-2022

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VLSI DESIGNS
Code Project Title
EMBEDDED POWER CONVERTER IEEE 2021-2022 BASE PAPER
IESEE-0019 A Decentralized Current-Sharing Controller Endows Fast Transient Response To Parallel Dc-Dc Converters
  
Abstract   Base Paper
IESEE-0022 Design Of Electric Energy Meter To Measure The Energy Consumption Enhanced With Iot Technology
  
 
IESEE-0017 Electronic Power Converter(Epc) Used For Dc Micro Grid Application With Sliding Mode Control Technique
  
Abstract   Base Paper
IESEE-0016 Emi-Based Current & Voltage Sensing For The Control Of Power Electronic Converters
  
  Base Paper
IESEE-0015 Improved Fault-Tolerant Method And Control Strategy Based On Reverse Charging For The Power Electronic Traction Transformer
  
  Base Paper
IESEE-0018 On Random Dynamic Voltage Scaling For Internet-Of-Things: A Game-Theoretic Approach
  
  Base Paper
VLSI DESIGN IEEE 2021-2022 BASE PAPER
IESVL-0071 28-Nm Latch-Type Sense Amplifier Modification For Coupling Suppression
  
 
IESVL-0086 A Modified Partial Product Generator For Redundant Binary Multipliers
  
 
IESVL-0135 A Novel Implementation Of Da Based Adaptive Filter Using Reversible Full Subtractor
  
 
IESVL-0138 An Efficient Design Of 16 Bit Mac Unit Using Modified Carry Save Adder
  
 
IESVL-0093 An Improved Dcm-Based Tunable True Random Number Generator For Xilinx Fpga
  
 
IESVL-0068 Approximate Error Detection With Stochastic Checkers
  
 
IESVL-0091 Area-Time Efficient Architecture Of Fft-Based Montgomery Multiplication
  
 
IESVL-0137 Da Based Lms Adaptive Algorithm Using Mcsa
  
 
IESVL-0130 Design A Novel Sram Architecture Using Sleepy Stack Technique
  
 
IESVL-0088 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
  
 
IESVL-0132 Design Of 12-Bit Digital To Analog Converter Using Cmos
  
 
IESVL-0058 Design Of An Area-Effcient Million-Bit Integer Multiplier Using Double Modulus Ntt
  
Abstract   Base Paper
IESVL-0133 Design Of Fir Filter Using Reversible Full Adder
  
 
IESVL-0134 Design Of Low Power High Speed Sram Architecture Using Sleepy Stack Approach
  
 
IESVL-0060 Design Of Power And Area Efficient Approximate Multipliers
  
 
IESVL-0059 Dual-Quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers
  
 
IESVL-0066 Energy-Efficient And Process-Variation-Resilient Write Circuit Schemes For Spin Hall Effect Mram Device
  
 
IESVL-0070 Energy-Efficient Vlsi Realization Of Binary 64 Division With Redundant Number Systems
  
 
IESVL-0090 High-Speed And Energy-Efficient Carry Skip Adder Operating Under A Wide Range Of Supply Voltage Levels
  
 
IESVL-0089 High-Speed And Low-Power Vlsi-Architecture For Inexact Speculative Adder
  
 
IESVL-0129 Implementation Of Bcd Adder Using Reversible Logic
  
 
IESVL-0064 Improved 64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction
  
  Base Paper
IESVL-0065 Low Complexity And Critical Path Based Vlsi Architecture For Lms Adaptive Filter Using Distributed Arithmeticalgorithm And Architecture Design Of Adaptive Filters With Error Nonlinearities
  
 
IESVL-0063 Low-Power Design For A Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
  
 
IESVL-0073 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic
  
 
IESVL-0061 Multipliers-Driven Perturbation Of Coefficients For Low-Power Operation In Reconfigurable Fir Filters
  
 
IESVL-0131 Optimization Of Lightweight Cryptography Using Present Algorithm
  
 
IESVL-0072 Power-Gated 9T Sram Cell For Low-Energy Operation
  
 
IESVL-0092 Probability-Driven Multibit Flip-Flop Integration With Clock Gating
  
 
IESVL-0069 Reconfigurable Constant Multiplication For Fpgas
  
  Base Paper
IESVL-0087 Reliability Enhancement Of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
  
 
IESVL-0062 Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing
  
 
IESVL-0074 Signature And Residue Testing Of Microprogrammable Control Units
  
 
IESVL-0067 Soft Error Rate Reduction Of Combinational Circuits Using Gate Sizing In The Presence Of Process Variations
  
 
IESVL-0136 Ultra Low-Voltage High Speed Schmitt Trigger Cmos Circuit
  
 
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